Parallel memory, multiple processing, variable word length computer



68 Sheets-Sheet 1 M TO R N H iNVENTURS RICHARDS CARTER WALT ER W WEL ZAug. 30, 1966 R. s. CARTER ETAL PERALLEL MEMORY. MULTIPLE PROCESSING,VARIABLE WORD LENGTH COMPUTER Filed rm. 23, 1963 25;; m Q Q A/ s; 22: Nmm 52:; r 12:55: am f6 :228: m 3 @2 w o: 1:2: :3 35 \J 3223 M. 23;; w s(w\ 3; EE; 1 N: :2: m: 02 32:25 :55; E e; fimw 31 5 2 E 2%? a 23:23 0::5: I; s

o: 3%: 8 3E 22 d =3: E;

3 m2: ZEIESQZ a 2N no: 525 oww 31 55 i B- 1966 R. s. CARTER ETAL3.270.325

PgRALLEL MEMORY. MULTIPLE PROCESSING, VARIABLE woan LENGTH COMPUTERFiled Dec. 23, 1965 68 Sheets-Sheet a FIG. 2 MEMORY CHARACTER SELECTIONDETAILS OH HO 5 FRUM MEMORY SENSE AMPLIFIER LATCHES (nor suowrn MAR 11mmsmcwm CH AR 2 EVEN cm 4 (Ex, cm ans CHAR 6 CHAR 8 CHAR 1 CHAR 3 CHAR 5CHAR 7 CHAR 9 1966 R s CARTER ETAL 3,270,325

nRALLaL MEMORIY. MULTIPLE PROCESSING, VARIABLE worm LENGTH COMPUTERFiled Dec. 23, 1963 68 Sheets-Sheet 3 FIG. 3

MEMORY CHARACTER SELECTION DETAILS (ODD CHAR) mom HEM SENSE MP W PHRSLATCHES (F|G.H4) 262 m mor suovm) m W dHMHWm an 264 214 20R3 a o cm 5 Wman 262 270 T 00R1 a 20a cm 4 c an 264 o mas a Y 0 cm c an NOb: s 1 W 000m a cmusn 1 0 5 CW 3 000 cm ens 210 L, 40R5- O 3 ems WrnBlT 0 H 208R7- a L CHARTWmBlT m 0 4 4oR5- a cmscan 0 o 2 EUR 1+? S: cm": 0 an 20aCHAR s an O SORT-P a f CHAR 1 1 an son9- 8 cm 9 Wm an 2551- aone a CHAR9 c BIT CHAR 94m Aug. 30, 1966 n. s. CARTER ETAL 3,270,325

PARALLEL) MEMORY. MULTIPLE PROCESSING, VARIABLE f WORD LENGTH COMPUTERFiled Dec. 23, 19615 68 Sheets-Shoat 4 4 PRIMARY CHANNEL GATE DETALS 0NF1 G 5 C G 1 (HG 55) 21s 210 zrs EVEN CHAR ans 5 (F|G.2 I

ms SCAN (mas) PRIMARY 302 CHANNEL MINUS SC AN (FIGv 86 ans ms. 2)

Aug. 30, 1966,.

PARALLEL MEMORY MULTIPLE PROCESSING.

WORD LENGTH COMPUTER 68 Sheets-Sheet 5 Filed Dec. 23, 1963 FIG.5

PRRMARY CHANNEL GATE DETAILS V IIL E NS m m on H C 2 2 W J 3 m m o w w Cflu A 8 4 2 4 9.. 6 1.. 1 2 4 L I 1 5 F e a W .M w 0 0 I a 1 z l I I 1 a1O ,O a

O a 1 NH 0 m 4 a we 8 9 i 9 9 2 2 0 0 D 0 1d 0 0 s H N i V aaaa aaa aaaa&a&& A r R 1 a 5 0 U 0 N F 3 S S 5 hmmmmm m wwmmumuu M L/N W L L W W H Hm m H H m m H P 4 m M P P M M M M M M O s 2 G 3 1 1 2 2 4 2 2 I l 2 2 0w P u G 6 MW mu Pu MM G G Pu m G G G "W G G IG||\C COG u C C PU C C C CC Pu c C llvrr 3 G Fu 6 00 M M m0 0 0 2 2 2 w w2m 2 l A: 1. w N w N N CN N N I N 82d: N 0 E D E D rt D CL 0 E D E 0 CL U 0T 2 L W D V D V D V UV D HI 0 V D V m n -u nu F. 0 F. 0 E 0 rr 0 E 0 E 0 E O G Dn m A U H EC1966 R s. CARTER ETAL 3,270,325

PARALLEL MEMORY. MULTIPLE PROCESSING. VARIABLE wom: LENGTH COMPUTERFiled Dec. 23, 1963 68 Shasta-Sheet 6 SECONDARY CHANNEL REGISTERS sr uwe) x *vffg. L 5 3 man 326 R o 1x 8 L necummi R *L E 8 325 Y/ mas) Sail!8 w a... ma 0 340 was] FIG, 7 z REGISTER DETAILS SET 2 REG 1 was) R55525)REGS r 530 /526 f a r/ 45 W WIT] 340 RLO 0 c & sL

350 O\ 326 a 5*? a B L PRIM a. s 4 A x REGISTER CHAN A L INPUT ens ens R0 was swoww me 51 m FIGS) 330 R 0 32 L. 7 1 8| 5 4 4 J RLO Aug. 30, I966s. CARTER ETAL 3 BAHALLEL ME Y. MULTIPLE: CESSING, VARIABLE k WORDLENGTH C UTER Filed Dec 23, 1963 68 Sheets-Sheet '7 SECONDARY REGISTERCONTROLS SERIAL SCAN cs4 cs2 A CYCLE m 0R TF4 g (H1155) (H653) (new:{F5633} m (H039) 304 +-j58 sen-j MATCH 8| are i m 404 (new 1 L J 5H 2565 P. I a V 354 REG msa O MATCH I:

350 543 N m 402 562 w I SET v a v MATCH REG nus-mew a (new ig; 380 344550 8 RESETHZ 556 t REGS 5 I 400 52 4 MATCH 4 O 5a2 a as 552 M 580 0 SETx 34s REGS I 408 MATCH 8 a I :c K 384 sao k an ass a 554 1F 40s lawn x81 l 355 H) EARLY 1966 R. s. CARTER ETAL 3,270,325

RARALLEL MEMORY. MULTIPLE PROCESSING. VARIABLE WORD LENGTH COMPUTERFiled Dec 23/3363 ea Sheets-Sheet 8 CASE 1 F|(;. 9 FIRST A CYCLE (SEEFIGS. 6,15 FOR mums) sum 350 x m on, CG2,tF4 f Z SECOND m R 0*524 R o\.(21s) PRIMARY cmwsns T 400 a /329 Y FIRST SE0 SE0 T HISMATCH, cs2 064 iCGLHH 402 R 0 325 2 USSEEFUL SECONDARY ems 8| 8| 4 u FUL PRIMARY cm (USEsums a) P X 4 SECDNDARY CHAN BITS CASE 1 FIG.1O SECOND A CYCLE (SEEFIGS. 6,15 FOR DETAILS) 40a msmcmcg -528 X SECOND msmmn, Z & c 2 4 a sFOURTH L L R 0 '524 s26 40s- 4 MISMATCH, PRIMARY tC EARLY cum BITS tD4 Ymum sec SEO T msmcu, s L cs2 cm i 00mm R 0* 2 USEFUL SECONDARY CHARS 8|8 4 USEFUL PRRMARY cm (UVERLAP souumv) Y FTHIRD X FSECOND SECONDARY CHANBITS 30, 1966 R. s. CARTER ETAL 3,270,325

fP ARALLEL MEMORY. MULTIPLE PROCESSING, VARIABLE wonn LENGTH COMPUTERFiled Dec. 23, 1963 68 Sheets-Sheet 9 FIG. 11 CASE 2 FIRST A CYCLE (SEEFIGS.6,45 FOR DETMLS) 404 /528 324 msmcu, sso v--- a x I Z CG2,tE1 a s 4HRST R D 52s :25 529 8 Y SEC SEC 1 cs2 cs1 *R 0 V V 4 USEFUL saconmm cm2 USEFUL PRIMARY CHARS mm A CYCLE) Y I SECONDARY cm ans CASE 2 SECOND ACYCLE F G 12 (won CYCLE BETWEEN 1ST. & 2ND. A mus) (SEE FIGS.6,16 FORowns) 404 msmncmc HISHATCH, z a X ms! CG2,tF4 a s 4 THIRD R 0 sso R o528/ 40s MISMATCH, t c PRIMARY 52s mu cm ans t0 4 a Y SECOND SE6 SE0msumu, I 002 cm 4 329 402 355 4 USEFUL SECONDARY cm (OVERLAP BOUNDARY)SECONDARY CHAN BITS 0, 1966 R. s. CARTER ETAL 3,270,325

PARALLEL MEMORY, MULTIPLE PROCESSING, VARIABLE WORD LENGTH COMPUTERFiled Dec. 23, 1963 68 Sheets-Sheet 10 CASE 3 FIRST A CYCLE (SEE FIGS.5,I5 FOR DETMLS) r a X Z S 4 s 4 L RLO a Y FIRST 550 SEC mcmsz s 4 0G1002 m 2 f 529 m q 4 USEFUL 5500mm CHAR a 5. 4 USEFUL PRIMARY CHAR cs4NEVER APPEARS W' x;

SECONDARY CHAN BITS CASE 4 [-19.14 SECOND A CYCLE (SEE FIGS, 6,15 FORDETAILS) 40a 4 4 MATCHJA Q MATcH,cs4,[ 0 7/550 8 X FIRST rEi Z FIRST 5 4R o 524 R o 326 406- mama, PRiMARY 121s:

CHAN ans +04 I Y SECOND SE0 SE8 MATCH,CG2, s cs2 cs4 +F4 402 529 R 0*-525 l7 2 USEFUL SECONDARY CHAR 2 USEFUL PRIMARY cm Y kSECOND X kHRSTSECONDARY CHAN BITS 1966 R. s. CARTER ETAL 3,270,325

VARIABLE PARALLEL MEMORY, MULTIPLE PROCESSING WORD LENGTH COMPUTER 68Sheets-Sheet 11 Filed Dec. 23, 1963 FIG. 15

SECONDARY CHANNEL GATE 420 4P SECONDARY CHANNEL SECONMRY CHANNEL PARITYCHECK SECONDARY CHA N N E L BIT S CYC LE FIG T1) A N DARD A YC L E 0 PSFIG 46 L 4 2 9 5 E C C G L HQ 16 SECONDARY CHANNEL REGS Fl C 61 S EC C G2 FIG 16 X CYCLE FIG 73 ADDHFSS EX IT FRCN CONSOLE A CYCLE (HC 701 SECCG 1 SEC CG 2 C G 1 Fl G, 53 1 NOT END A (FIG. 78 IAT+ CG 2 FIG. 5 3 JAug. 30, 1966 R. s. CARTER ETAL 3,270,325

PARALLEL MEMORY, MULTIPLE PROCESSING, VARIABLE WORD LENGTH COMPUTERFlled Dec. 23, 196.3 68 Sheets-Sheet 12 FIG.17

RETURN CHANNEL 2ND CHARACTER GATE g F 1 a (8) B CYCL IG N SEC CHANHHHS)O Y RETURN CHANNEL 2ND CHAR I CYCLE (H859) (a) (s) 452 8 PRIMARY CHANNEL3 8| 0 ADD (FIG 45) a CYCLE (mmfi 419 O XCYULE (H073) 1966 R. s. CARTERETAL 3,270,325

PARALLEL MEMORY. MULTIPLE PROCESSING. VARIABLE WORD LENGTH COMPUTERFiled Dec. 23, 1963 68 Sheets-Sheet 1s F'GJB RETURN CHANNEL 1ST CHAR.

REGISTER 8| GATE 1 E EARLY 454 4sa--- A. 0 L1 OPERATOR SET 465 }FROMcousou NOT snovm m OPERATOR RESET 0 PROGRAM RESET (FIG, 39)

4621 /450 T 8 s Wm -R 0 Wm v S T A a L RETURN CHANNEL L R O- T RETURN2ND CHARACTER BTTS l CHANNEL (FTGTT) 3 mom a BTTS R o E M S T 4 a L R 04 T a s 1 3 L 7 S 1 1 L R O- 1 462 Aug. 30, 1966 R. s. CARTER ETAL3,270,325

PARALLEL MEMORY. MULTXPLE PROCESSING, VARIABLE WORD LENGTH COMPUTERFiled Dec. 23, 1963 68 Sheets-Sheet 14 FIG.19 MEMORY INPUT 000/ EVENCONTROLS 5 52 REGEN MEM mesa) -V PROGRAM RESET (m; as) 0 REM] MEMORY(FIG 34 LOAD MEM (FIG 5a 512 555 554 PLUS SCAN a 51 4 5 0 cm ms 55) 7 f520 52s O LOAD EVEN CHARS 302 R L 0 REGEN EVEN ems Mmus smmaam a. T

PLUS scan a 518 5 cs 2 7 t 522 506 [525 O SL4 LOAD 000 cms MINUS SCAN 8R T REGEN ODD CHARS cs 4 f A LT ER N AT I V E F ORM O F F I G. 1 9

M M 8 1 RECEN EVEN mus SCAN a LOAD EVEN cc 2 NOT PROS RESET um READ MEMPLUS scan REGEN 000 MINUS 5 0 2 22 LOAD 000 nor PROS RESET NOT READ mamR. s. CARTER ETAL 3,270,325 PARALLEL MEMORY. MULTIPLE PROCESSING,VARIABLE WORD LENGTH COMPUTER G8 Sheets-Sheet 16 O ""2 wDn ulunn MR nHem mm m W 3 M I IC f 2 R n 0 O III .i liillll m E fi L l EE HR 8 J FM68 k. H 4 PM M W m I \O w m a A r m m1 5 w J; 1 2 4 4 w H M 1 n r z s AA d 4 4 7 m a u 1 4 zsgwa m m m m8 m8 E CL L13 V 0 a a C N w it H mfimYEEIEL m J l 2 Aug. 30, 1966 Filed Dec. 23, 1963 Aug. 30, 1966 IARALLJELMEMORY. MULTIPLE PROCESSING, VARIABLE WORD LENGTH COMPUTER Filed Dec R.S. CARTER ETAL 68 Sheets-Sheet 1'7 REGEN CHAR 0 (H922) soo cmo 420 FIG.24 240- PLUS SCAN (H986) Wm\ 8 502 an M0 MINUS SCAN (FIG 86)/ 23s v LLOAD smommn A 8 0 wm 412 500 REGENERATIONUROM ZNDCHAR MEMORY SENSE AMPL'W/ h. a LATCHESNOTSHOWN) 232 CHARO 410 501 0 8| -h an 480 151cm E 8 O C4r 2ND CHAR 2 'c F. INHIBIT a CHAR 0 RETURN 252 ans T0 CHANNEL MEMORYmes. 5 men nus) CHAR U waves T suowm 411 1 15mm l ,1

Y a O 2 2m) CHAR L 500 J,

5 8 ?%EEk M M L 252 LATCHES-NOT SHOWN) ammo mn 5o1 T 8 480 151 CHAR T a0 4 J 2ND CHAR 412 1956 R. s. CARTER ETAL 3,270,325

PARALLEL MEMORY, MULTIPLE PROCESSING, VARIABLE WORD LENGTH COMPUTERFiled Dec. 23, 1963 68 Sheets-Sheet 18 FIG, 25 BASIC TIMING CHART F-ABOUT 20o NANO SECONDS PROGRAM msnmcss START (H039) RAW use (H026) mt 1STOP LATCH (H040) B61 g I I 862 g I cP'smmm i1|2|5141lzhiahlzala;

FIG. 26

OSCILLATOR m srwmcsamn ./74fl MA a 750 u 154 GP H030, O MACHINE ISSTOPPED T12 cum RESET mm L,

(F1642 8 CP1(F|G30)-" M752 use A 050 DELAYED i so wv 0 590/ RAW 05C Aug.30, 1966 R s. CARTER ETAL 3,270,325

PARALLEL MEMORY. MULTIPLE PROCESSING, VARIABLE WORD LENGTH COMPUTERFiled Dec. 23, 1963 68 Sheets-Sheet 19 BINARY GATES FOR CLOCK 0500ELAYEnlr|c2e1L- 1 'f fi B'MRY 1 nm BINARY GATE 1 auow NOT CHECK a I*' inew FAUU R 356 608 BINARY GATE 2 556 1 a. 8 H3562 8. X PROGRAM 1 2 3RESET H Y: f (FIG, 59) n 5 f l 7 a E a l: a HOLT BINARY GATE 2 j 4 355 56 02 P- usu FIG.28 BINARY GATE 2 GENERATION CHART OUTPUW LATCHES T R05614556 m MED ou REMARKS 1- O F Q OFF {WITH RESI,2FU1.LOWS 2 i OFF OFF osc,0HERS,UNAFFECTED 3 OFF 0F? EFF 7N0 NYE r 4 on on V2 ore; s L I H fi m 50N g OUTPUT REVERSES /5Qfl /2UNLATCH] B+-++-+-+- OFF qry 5 7 OFF OFFTHIS HLQLUJIAL i2 LFIWE 13 OFF OFF OFF ii iJil,.E.LL. 14+--++++-0u on15++++++-- 1e+-++---+-+ OFF 0:4

Aug. 30, 1966 R s. CARTER ETAL 3,270,325

PARALLEL MEMORY MULTIPLE PROCESS ING VARIABLE WORD LENGTH COMPUTER FiledDec. 25, 1 963 68 Sheets-Sheet 2o CLOCK PULSES 1-4 586 801 i 606 a CF!050 (F1826) 7/ 0 516 1 600 8 CP 2 l 51? 881 a A514 CH BINARY (mix/4 604(F v c 27 1 T 2 ew 4 602 a s19 C P MAIN CYCLE CLOCK ILLUSTRATION 622 DET A I L 5 0" FIG 3 2 LAST (new: A

EARLY PROGR A u RESET (new NOT PROGRAM RESET FIG 59 624 2 NOT LOADMEMURY CYCLE S LOAD HE MORY CYCLES

1. IN A DATA PROCESSING SYSTEM HAVING MEMORY MEANS WHICH WILL DELIVER APLURALITY OF DATA BIT GROUPS UPON EACH ACCESS; EACH GROUP BEINGSPECIFICALLY ADDRESSABLE BY THE DATA PROCESSING SYSTEM; AT LEAST A FIRSTPART OF A WORD TO BE HANDLED BY PROCESSING MEANS OF SAID PROCESSINGSYSTEM BEING MANIFESTED BY AT LEAST ONE OF SAID GROUPS IN DEPENDENCEUPON THE ADDRESS OF THE FIRST GROUP IN COMPARISON WITH THE ADDRESSES OFALL THE DATA BITS GROUPS DELIVERED BY SAID MEMORY MEANS IN THE SAMEACCESS THEREOF; A WORD BEING AT LEAST ONE GROUP; SAID DATA PROCESSINGSYSTEM HAVING A PROCESSING CAPACITY IN EXCESS OF A SINGLE GROUP; SAIDDATA PROCESSING SYSTEM BEING CAPABLE OF GENERATING AND RESPONDING TOSUCCESSIVE CYCLE SIGNALS SO AS TO PERFORM SUCCESSIVE CYCLES OF OPERATIONAS WILL ACCESS SUCCESSIVE MEMORY GROUP SETS IN SAID MEMORY MEANS; SAIDMEMORY GROUP SETS EACH CONTAINING AS MANY GROUPS AS THE LESSER OF THENUMBER OF GROUPS RELATED TO SAID FIRST GROUP AND THE CAPACITY OF SAIDSYSTEM; A BOUNDARY ADJUSTING MEANS COMPRISING: ADDRESSING MEANS FORGENERATING, IN A FIRST CYCLE, MANIFESTATIONS OF AN ADDRESS WITHIN SAIDMEMORY WHEREIN THE FIRST GROUP OF SAID FIRST WORD IS STORED, SAIDADDRESSING MEANS EXERCISING CONTROL OVER SAID MEMORY MEANS SO AS TOCAUSE SAID MEMORY TO DELIVER A PLURALITY OF GROUPS, INCLUDING THE GROUPRELATED TO THE ADDRESS SPECIFIED BY SAID ADDRESSING MEANS, IN ONE ACCESSOF SAID MEMORY; SAID ADDRESSING MEANS ALSO CAPABLE OF GENERATING THEADDRESS OF A GROUP OTHER THAN SAID FIRST GROUP; ANALYZING MEANSRESPONSIVE TO SAID ADDRESSING MEANS FOR DETERMINING A MAXIMUM NUMBER OFGROUPS RELATED TO SAID FIRST GROUP WHICH ARE DELIVERED BY SAID MEMORYMEANS AT EACH ACCESS THEREOF; EXTERNAL STORAGE MEANS RESPONSIVE TO THEGROUPS DELIVERED BY SAID MEMORY MEANS FOR STORING A PLURALITY OF GROUPSRELATED TO GROUPS SPECIFIED BY SAID ADDRESSING MEANS; AND MEANSRESPONSIVE TO SAID ANALYZING MEANS FOR CAUSING AN INITIAL ACCESSRESPONSE, OF ONE OR MORE INITIAL MEMORY ACCESSES, TO OCCUR, ASNECESSARY, SO AS TO PROVIDE SUFFICIENT GROUPS TO SAID EXTERNAL STORAGEMEANS TO UTILIZE THE PROCESSING CAPACITY OF SAID SYSTEM DURING APROCESSING CYCLE FIRST FOLLOWING SAID INITIAL ACCESS RESPONSE, SAIDPROCESSING MEANS PROCESSING AT LEAST SAID FIRST GROUP AFTER SAID INITIALMEMORY RESPONSE.